With the imaging appliance revolution underway along with the advance of electronic industry, the need for more advanced display devices is increasing and the flat-panel mobile display industry is searching for a display technology that will revolutionize the industry. The need for new lightweight, low-power, high brightness, and extensive endurance display devices has pushed the display industry to revisit the current flat-panel digital display technology. Compared with other display technologies, the LED display has the following advantages, such as self-luminescence, super-thin appearance, high brightness, high luminance efficiency, short response time, power saving, wide temperature tolerance, flexible panel, and so forth. Therefore, the LED display is believed to be the major trend of the display market for the coming generation.
Generally, it is common to drive an OLED display by using the row scan technology, which applies the three-phase driving method. As shown in FIG. 1A to FIG.1D, for each column, there are phases of Dis-charge, Pre-Charge, and Current On, and for each row, there are phases of Reverse Bias and Current Sink.
As seen in FIG. 1A, the successive phases of an active column are sequentially addressed as following:                Dis-Charge phase 11: for eliminating the electricity previously stored on an LED of the active column;        Pre-Charge phase 12: for compensating the parasitic capacitance of the LED so as to enable the LED to have a preferred initial value for the Current On phase 13 successive to the Pre-Charge phase 12; and        Current On phase 13: for conducting electric current to the LED.        
As seen in FIG. 1B, the successive phases of a non-active column are sequentially addressed as following: Dis-Charge phase 14; Dis-Charge phase 15; and Dis-Charge phase 16; during which the anodes of the LEDs of the non-active column are grounded since the LEDs are not to be activated.
As seen in FIG. 1C, the successive phases of an active row are sequentially addressed as following: Current Sink phase 17; Current Sink phase 18; and Current Sink phase 19; during which the cathode of the LEDs of the active row are grounded for conducting a forward bias current thereto.
As seen in FIG. 1D, the successive phases of a non-active row are sequentially addressed as following: Reverse Bias phase 20; Reverse Bias phase 21; and Reverse Bias phase 22; during which a reverse bias is provided to each of the LED of the non-active row for preventing the conducting of current and thus enabling the LEDs to endure longer operation.
FIG. 2A illustrates a schematic architecture of a panel of passive-matrix LEDs, which is adversely influenced by the effect of parasitic capacitance. As the panel of passive-matrix LEDs is first activated, the driver drives the passive-matrix LEDs to enter their first phase, i.e. the Dis-Charge phase for the active columns and non-active columns, and the same time that the columns S1˜S4 are grounded while the row R1 is an active row and the rows R2 and R3 are non-active rows that are connected to a reverse potential of Vrev as seen in FIG. 2B. That is, at the moment shown in FIG. 2B, the rows R2 and R3 are not being scanned but still the LEDs of the two rows R2, R3 are being charged by the reverse potential of Vrev. In that the use of the reverse potential of Vrev is considered as a waste of energy for charging those non-active LEDs.
Assuming that the column S1 is an active column and the columns S2, S3 and S4 are non-active columns and all are driven to enter their second phase, which is shown in FIG. 2C, the column S1 is enabled to enter the Pre-Charge phase while the row R1 is grounded and the rows R2, R3 are connected to the reverse potential of Vrev. Therefore, the LED at the intersect of R1 and S1 is charged to a pre-charge potential of Vpre while the LEDs on the column S1 of rows other than R1 are also being charged, i.e. the Vpre connected to the column S1 also charges the capacitors of the LEDs at the intersect of R2, S1 and R3, S2, which are addressed as C2-1 and C3-1. However, since both the C2-1 and C3-1 have the reverse potential of Vrev, it requires a longer charging time or a higher voltage to complete the Pre-Charge phase, moreover, as the more the rows exist in the panel, the more sever the effect of parasitic capacitance such that the loading of the pre-charge circuit is increasing as to consume more power.
As the column S1 enters the Current On phase as shown in FIG. 2D, the column S1 acting as an active column is conducting a current to the panel of passive-matrix LEDs while the columns S2, S3 and S4 and the row R1 are still grounded and the rows R2, R3 are still connected to the reverse potential of Vrev. At the moment of the Current On phase that is capable of charging the capacitors of the column S11 to a potential of Vcon, if Vcon<=Vrev, the potentials of the C2-1 and C3-1 will be—(Vrev-Vcon) such that the potentials at the ends of R2 and R3, i.e. Vr2 and Vr3, are increased by charge pump effect enabling both Vr2 and Vr3 are larger than Vrev. Nevertheless, those surplus potentials will be discharged by the ESD protection diode installed in the driving circuit so that the potentials at the ends of R2 and R3 are recovered to Vrev. Thus, it is noted that the increasing of potential along with the successive ESD discharging is a waste of energy.
After the Current On phase is completed, the present scan duty is completed and the next scan duty is initiated that the row R2 is being scanned instead of the row R1, that is, the column S1, S2 and S3 and the row R2 are grounded while the rows R1, R3 are connected to Vrev, where the transition of a capacitor of the passive-matrix LED is shown successively in FIG. 3A, FIG. 3B and FIG. 3C. Similarly, the charge pump effect also causes energy waste in this next scan duty.
Form the above description, it is noted that an improvement to the conventional panel of passive-matrix LEDs is greatly required.